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1 agilent technologies E2930B exerciser and protocol analyzer for pci-x 2.0 technical overview key specifications support for pci-x mode 1 and 2 (mode 2 up to 266 mt/s ddr) 64 bit data and addressing exerciser (option #300) with full capabilities, including split transactions, 4 mb of data memory (512k x 64 bit) and real-time data generator unidirectional data path verification real time data compare pci-x mode 1 and 2 compliant 64 pci-x protocol rules usb 2.0 controllable in-system through pci-x interface pci-x state analyzer with 4m state trace memory realtime performance analysis system validation pack (option #310) with compliance tests c-api (command application programmming interface) gui (graphical user interface) tcl interface agilent patented protocol permutator and randomizer technology ?
2 agilent E2930B exerciser and protocol analyzer for pci-x 2.0 the exerciser and protocol analyzer for pci-x 2.0 mode 1 and mode 2 provides r&d and qa engineers with a fast and predictable way to debug, optimize and validate pci-x based designs, like servers, motherboards, chip-sets, raid systems or network interface cards. the modular test card combines a pci-x protocol checker, a pci-x exerciser (option #300) with full requester and completer capabilities to generate any kind of pci-x transfer and a pci-x state logic analyzer. individual software modules address specific needs during design bring up, design validation and compliance testing. verification of pci-x protocol compliance the E2930B f eatures a pci-x protocol checker, which r uns constantly, checking for pci-x protocol rule violations in real- time. in total, 64 prot ocol r ules are checked concur rently. all r ules are derived from the pci-x 2.0 specif ication. thus, simply plug- ging the E2930B into a pci-x system allows you to check for pci-x prot ocol com pliance. the E2930B reports a list of all the errors that have occurred. for the purpose of debugging, the prot ocol checker can be used to trigger either the state logic anal yzer or an external logic anal yzer. also, each individual prot ocol rule can be masked. bring up and debug with its capabilities in generating pci-x 2.0 traffic and simultaneously analyzing the generated traff ic, the E2930B is perfectly suited for bring up and debug of pci-x 2.0 and pci-x 1.0 systems. the anal yzer displays, with several levels of hierarchy, the captured trace and helps the engineer to debug and understand what is happening in the system. the g raphical user interface supports the user in setting up various types of transactions and programming the anal yzer. predictable system and chip validation the E2930B pci-x exer ciser (option #300) features a fully controllable requester and completer, real-time data com pare and har dware support for the agilent patented prot ocol permutation and randomizing technique and the patented undirectional data v erification method. this allows engineers to validate and stress the pci-x system with specific and fully repeatable t est cases. the testcard can aut onomously and repeatedly generate a series of programmable transactions, whilst generating prot ocol permutations in hardware and checking for data integ rity errors and prot ocol violations. key capabilities for t his use model are: generates deter ministic traffic exhaustive cov erage of prot ocol corner cases through a patent- ed protocol permutator and randomizer (ppr,option #320) technology checks for data integ rity and protocol err ors. the benef its of using this appr oach are: the state of bridges is not affected through traffic that may be needed to setup the testcard, because the testcard can run t ests aut onomously and predictably . very high cov erage thr ough hw permutation of test cases (more t han 100 000 test cases or transactions per second). very short test ex ecution time. multiple testcards can be synchroni zed across multiple buses or even acr oss multiple syst ems by using bus event based triggering or external trigger cabling. efficient design debugging to get an insight into y our syst em, a simple click of the mouse is all that is needed to setup a specific trigger or the state anal yzer. the state anal yzer offers im pressive trigger and storage qualif ier capabilities making it easier to find com plex error conditions. besides conventional pattern terms for all pci-x 2.0 signals, an additional bus observer makes the current bus status (e.g. address phase, attribute phase, dat a phase, idle phase et c.) transparent, and thus sim plif ies the setup of trigger conditions. combining additional error pattern terms, exter nal trigger inputs and trigger sequencer capabilities, t he E2930B gives you the ultimate power to capture the data you need. system benefits easy pci-x 2.0 system e valuation ability to w ork in pci-x mode 1 and mode 2 windows based gui for interactive use state analyzer for pci-x 2.0 exerciser for pci-x 2.0 stresses your sy stem's corner cases predictably and repeatedly easy system validation using ready- to-run tests over 1,000,000 t est cases in less t han 5 seconds 1 programmable in-system c-application programming interface tcl inter face system overview the E2930B is a short pci card, which can simply be plugged into the system under t est. it is controlled by an int eractive graphical user inter face from a cust om-written c program, or from a tcl interface (option #320 required). the sof tware can either be inst alled on the system under test itself - contr olling the card through the pci-x 2.0 system bus, or on an external host - control- ling the card by usb 2.0, designed for a high data transfer speed. 1 test case @133mhz = (50 clocks delay + avg. 250 clocks for 2k bursts) *7.5ns = 2.5us. thus, 1,000,000 test cases need = 2.5s + 2s setup time.
3 pci-x protocol checker the E2930B basic conf iguration supports the pci-x 2.0 prot ocol checker which checks over 64 protocol rules in real-time. each rule can be individually masked to suppress the triggering of known problems. the rules are derived from the pci-x 2.0 specif ication 2 , and are designed to find any possible violations of the pci-x 2.0 protocol. when a protocol violation is detect ed, the prot ocol checker can: store the r ule number of the first (non-masked) violated rule list all f ound protocol errors accumulate the number of violated rules directly trigger the pci-x 2.0 state anal yzer?s trace memory. trigger exter nally connected logic anal yzer or additional E2930B cards (or even e2929bs for cross bus trigger ing if necessary). 2 pci-x addendum to the pci local bus specification revision 2.0, july/29/2002 figure 1. E2930B figure 2. protocol checker
4 state analyzer the pci-x 2.0 state anal yzer observes all signals (except jtag) specified by the pci-x 2.0 specif ication for a 64 bit 66/100/133 mhz system. in detail, the anal yzer captures: 4m samples all 64 bit pci-x address/data signals pci-x 2.0 prot ocol errors bus observer to decoded bus state signals, time aligned to the bus signals active requester and com pleter signals, aligned with the bus signals for easy identif ication of transactions invol ving the exerciser 4 signals fr om the trigger i/o connector. storage qualification a simple push-button storage qualif ier selects storage to opti- mize the use of the state anal yzer memory, depending on the level of detail you need. for exam ple: store all states suppress idle cy cles suppress wait cy cles suppress data transfers by pattern term. the st orage qualif ication can also be user prog rammed, using the trigger sequencer. 11 pattern terms the E2930B pro vides a total of 11 pattern terms: 4 pattern terms m onitoring all pci-x 2.0 bus signals (excluding jtag si gnals) and trigger inputs 1 pattern term monitoring the protocol checker error signals, spilt transaction err ors and data compare errors 6 pattern terms m onitoring the bus observer. to set up a pattern, each individual bit can be masked 0/1/x. for bit f ields, such as c/be, all bit combinations can be defined individually. figure 3. waveform viewer: bus cycle lister and transaction lister with cross references. bus observer for easy triggering the bus observer allows easy triggering for t he engineer's daily tasks by defining one sim ple pattern term. the bus observer automatically det ects: idle bus cy cles address cy cles, the 1st and 2nd half of dual address cy cles respectively attribute phase transactions to 32 or 64 bit address space decode cy cles, decode speed a/b/c/subtractive data cycles 32 or 64 bit transfers target responses as claim transactions, single data phase disconnection, disconnection of next address boundary, abort split transactions/response waits and retries master aborts terminated unsuccessful transactions. pci-x mode
5 figure 4. trigger gui 16 level trigger sequencer for extended trigger scenarios, the E2930B features a trigger state machine, which handles up to eleven pattern terms, one termination counter (pre-load and decrement) and up to 16 levels of trigger sequencing pattern terms can be combined with logical operations and, or and negation. the ter mination counter can be pre-loaded and decrement. flexible trigger points for maximum f lexibility, the trigger can be placed at any position in the trace memory . external trigger i/o 4 trigger i/o signals provide a way to synchronize betw een multiple pci/pci-x test cards of the e2920 series or ot her test equipment like a general-purpose logic anal yzer. prog rammed as input pins, they are observed by the state anal yzer and are available as part of the pattern terms. gui/c-api control or tcl scripting language interface the pci-x 2.0 state anal yzer comes with a windows based gui (graphical user inter face), a cli (command line inter face) and a tcl int erpreter window. the command line interface (cli) and the tcl int erpreter window allows you to interactively control the pci exer ciser and anal yzer by entering command functions that correspond with the functions provided by the c-api. the cli can also pr ocess batch files of concatenated command functions.
6 exerciser (option #300) the a gilent E2930B has an optional on-board 64 bit pci-x 2.0 exer ciser. the exer ciser operates in mode 1 and mode 2 with ddr and can emulate and force practically any beha vior of a pci-x 2.0 de vice imaginable - including bl atant pr otocol violations. this means t hat the exerciser is able to send and respond to specif ic traffic patterns including t est error recovery systems. the exer ciser comes with a graphical user inter face (gui), a command line interface (cli) and a tcl inter face. as an option, the exerciser can be controlled from a c-api (option #320). the exerciser f eatures: one requester-initiator with two requester queues one com pleter with f our completer queues to handle independent split-transactions one requester- target handling up to 32 open requests. requester and com pleter are fully programmable, operate independently of each ot her and are able to handle: 32/64 bit data transfers 32/64 bit addressing programmable delays between transactions block length up to 4gbyte all 16 pci-x 2.0 command types, including de vice id messaging commands. configuration space the E2930B pro vides conf iguration space, which is fully programmable. default values (cust omizable) are st ored in an eeprom on- board and are used to initialize the conf iguration space when the po wer is swit ched on. the conf iguration space can be disabled, making the card invisible to bios or o/s conf iguration r outines. thus, anal ysis t ests are possible wit hout having any eff ect on the de vice or system under test. the E2930B has the full 4096 bytes of conf iguration space required by the pci-x 2.0 specif ication. requester initiator data block the requester initiator data block settings define which address space is accessed, and to where data is moved. up to 256 block transf ers can be defined and performed in a linear sequence by one of the two transfer queues. each block specif ies: the bus command seen on c/be[3::0] in t he address phase. all valid pci-x commands are supported the 64 bit bus address the byte enable value (c/be[3::0] / c/be[4::7] the start address of the internal data memory the number of bytes to be transfer red (1byte to 4gb) if the real-time data com pare for incoming data should be activated the start condition for the transfer (immediately or wait for event) which transfer queue the data is passed thr ough. requester initiator behavior the requester initiator beha viors are set to sp ecify the pci-x transfer behavior per sequence. up to 256 attribute entries, which can be setup as linear sequence or repeat loops, are allowed. the attributes control: 32 or 64 bit data access inser tion of 1 to 65535 clock cycles delay betw een transactions the transfer queue to be used if an automatic or cust omer defined tag (0..31) is used the specific sequence length for the transfer (1 to 4096 byte) automatically r ounded up to the next qword boundary the n-th adb where the requester initiator disconnects (1 to 32) perform 0 to 4 address steps how many clock cy cles after the address phase req# is de-asserted (0 to 2047) how often the current transfer attributes are used (repeat value 1 to 256). architectural overview the exerciser is based on two main ideas. fi rstly, defining requester initiator data blocks, describing ?what? data should be transfer red and secondly, def ining a requester initiator beha vior, describing ?how? t he transfer should be ex ecuted. for the requester initiator, up to 256 blocks of data transfers can be set up . in addition, requester initiator behaviors are set up, specifying how t he requester initiator int ends to transfer the data blocks over the pci-x 2.0 bus. if any com pleter target replies to a transfer and requests a split transaction, the requester initiator data block attributes are moved internally to a split transaction map for further use. the transaction map can manage up to 32 open split transactions. when completing split transactions, the requester target beha viors are used to control the transfer. the completer t arget beha vior attributes def ine how the completer target of the E2930B acts. the com pleter t arget can manage up to 4 split transaction queues. it is also possible to fully control initiating the completion of split transactions. the com pleter initiator beha vior attributes are used to prog ram this. the programmable transaction scheduler decides whet her completer or requester transaction is performed. all data comes or goes through the on-board data memory or from the on- board real-time data generator.
7 figure 5. E2930B option #300 pci-x exerciser architecture latencies between requester initiator transactions the lat encies betw een transactions can be varied using requester initiator behavior pr oper ty. the minimum lat ency is in general 2 clock cycles (for mode 1 1 clock cycle) - including any sequences of read/write w here real-time data compare is invol ved. a possible exception is if the m ost recent transaction is a read/w rite trans- fer into data memory and the subsequent transaction is a write out of data memory. in t his par- ticular case, the lat ency is 10 to 20 clock cy cles. please note t hat it is assumed t hat the master does not need to disconnect bef ore the byte count of the cur rent sequence is transfer red and that wait cycles are added if required by the pci-x specif ication. requester target behavior the requester beha vior attributes are set to specify the pci-x 2.0 transfer behavior per transaction if a completer requests the completion of a split transaction from a requester initiator. up to 256 attribute entries, which can be setup as linear sequence or repeat loops, are allowed. the attributes control: the decode speed used (a 3 /b/c) ackno wledgement of 64 bit data transfers the number of initial lat ency clock cycles (3 to 34) the behavi or after initial latencies, either accept transfer, disconnect, signal retry or abort how often the current beha vior is applied (repeat value 1 to 65536 ). completer target behavior attributes the completer t arget beha vior attributes give full control over the E2930B completer t arget behavior, and define ho w it reacts to a request. up to 256 attribute entries, which can be setup as linear sequences or repeat loops, are allowed. the attributes control: the decode speed used (a 3 /b/c) ackno wledgement of 64 bit data transfers the number of initial lat ency clock cy cles (0 to 31) the behavi or after initial latencies, either accept transfer, signal a single data phase, retry or abort the behavior in subsequent data phases, eit her accept all subsequent data phases, disconnect after 1 to 2047 data phases signaling a split response, either by identifying an address value or range in the address phase, the decoder accessed, or by a subset of all 16 possible pci-x commands the split transaction queue to be used how often the current behavior is applied (repeat value 1 to 65536). configuration space and decoders in total, the E2930B f eatures 6 decoders: one st andard conf iguration space decoder, fully customer programmable one device id message decoder three pr ogrammable t arget decoders (six bars) that can either hold up to three memory spaces (64 bit) or two memory spaces and two i/o spaces simult aneously decoders can decode up to 4 gig of address space one decoder to access the 64kbyte expansion rom additional 4k extended config space all decoders can be switched off by a dip-switch on the E2930B, making the card com pletely invisi ble to the system under t est. completer initiator behavior the com pleter initiator beha vior attributes are set to specify the pci-x transfer behavior per transaction if a completer starts to complete a split transaction. up to 256 behavior en tries, which can be setup as linear sequence or repeat loops, are allowed. the attributes control: the split transaction queue to be served the start condition for this transfer 32 or 64 bit data transfer the number of clock cy cles inserted bef ore req# is asserted (1 to 65535) the number of clock cy cles before req# is de-asserted (1 to 2047) the number of address st eps (2 to 6) how often the current transfer attributes are used (repeat value 1 to 256) disconnect at n-th adb (1 to 32). 3 decode speed a is supported up to 66 mhz
8 completer target latencies the initial lat encies can be programmed with the com pleter target behavior attributes. depending on the selected decode speed and address phases, the test card automatically adds the needed number of wait states to achieve the def ined initial lat ency. a minimum of one wait cycle is always added when using decode speed b or c and a minimum of two wait cycles are needed with decode speed a. data memory the E2930B exer ciser option #300 features a 4mb (152k x 64 bit) programmable read/write data memory. requester and com pleter share the memory. the address decoders can selectively address it. the data memory can: store data from read/write transfers be mapped to any pci-x address space. data generator inst ead of using the data memory, the on-board data generator can be used. wit hout initial lat encies, the generator can generate a data pattern, deterministically linked to the data address. combined with a second exer ciser card and the real-time data com- pare f eature, long-term load stressing on any data path can be performed while errors are detect- ed in real-time (f igure 3). the generator f eatures the f ollowing patterns: walking ones or zeros ground bounce count up (unique data) pseudo random pattern (unique data).the count up and pseudo random pattern are unique up to the length of 1m quad words (4mb). the data uniqueness is derived out of the lower bit 2 to 22 of the bus address. real-time data compare real-time data com pare can be performed either on: memory: when data is written to the memory it is com pared against the actual memory content data generat or: based on the data address the generator calculates the expected data and compares it with incoming data. exerciser graphical user interface the graphical user interface gives you an easy way to setup and control the exerciser. master conditional start the master conditional start window allows you to set up the start conditions for the master traff ic. f ollo wing a run command, the master can be progra mmed to start: immediately triggered by a pattern. target decode window the t arget decode window lets you conf igure the t arget address decoders. as w ell as conf iguring the programmable decoders for the exerciser's on-board memory, you can individually enable or disable the decoders for conf iguration space and expansion rom. you can also store the current settings as defaults, which will t hen be used f ollo wing all subsequent power cy cles or pci-x resets. error injection capabilities the E2930B is capable of injecting error conditions into a system including generating inverted parity (par and p ar64), signalling a parity error (perr#), a system error (serr#) in a specified phase of the transaction, or ecc errors. figure 6. exerciser gui with all five different behavior editor windows
9 figure 7. undirectional data path verification figure 8. exerciser generic settings configuration window the configuration window lets you view and modify the current conf iguration space settings of the pci-x 2.0 exer ciser and anal yzer card. you can also store the current settings as defaults, which will t hen be used f ollo wing all subsequent power cy cles or pci-x 2.0 resets. data memory editor the data memory editor lets you view and modify the contents of the exerciser's on-board memory. this allows you to def ine the data content for master write transfers or target read accesses to the card, as well as allowing you to view the data received from master read transf ers or target write accesses. the data can be viewed in hex for mat, big or little endian, and 8, 16, 32 and 64 bit size. data generator setup window the data generator setup window allows you to select the algorithm to be used for data generation.
10 agilent system validation package, svp (option #310) the system v alidation p ackage is ready- t o-use sof tware package, which performs system stress tests during t he validation of serv ers, workst ations, pcs, or other pci/pci-x based systems. with its easy- to-use windows- based gui, it sim plif ies t est development on setup for engineers and allows easy test execution by t echnicians. choosing the agilent e2925b, e2928a, e2940a, e2929b and E2930B option #310 adds the system v alidation p ackage to your hardware order. target application the system validation p ackage programs and contr ols multiple pci/pci-x exerciser and anal yzer test cards of the e2920 pci series to creat e realistic application system traff ic. the t est card appr oach allows you to set up fully predictable traf fic scenarios and gives you measurable test coverage and test predictab ility. used for validation of pci/pci-x based systems and silicon, it enhances the traditional test method of using off-th e-shelf pci/pci-x cards. outstanding test coverage today?s validation test met hods typically lack time eff iciency and repeat able execution of critical system traffic scenarios. hot mock -up t ests, which use off-the- shelf pci cards to load a system- under- t est and wait until an error occurs, are the typical test appr oaches used today. now the system v alidation p ackage executes such types of system critical tests wit hin minutes, simply with a mouse click. ppr, the key technology agilent ?s patented prot ocol permutation and randomizing (ppr) technology is the key to predict able and repeat able test coverage.ppr is technology that allows permut ation of the pci/pci-x protocol and traffic in a determinisitic way. thus, system critical test patterns are not only transfer red between diff erent system com ponents,but also automatically permutate to achieve all possible traffic scenarios. stress all critical data paths by plugging the pci/pci-x exerciser and anal yzer test cards in each individual pci/pci-x bus of your system under test, the software is able to aut omatically test and stress data paths within your system (see f igure 9). a small ex ecut able running on the system cpu(s)allows testing within the whole system, not only the i/o syst em, while tests are run from an external controlling host. system validation package/system test library benefits fully controlled t est envir onment for validation of serv ers, workst ations and pcs predictable t est cov erage repeatable t est scenarios documented t est results. testcard testcard testcard pci peer primary bus 1 pci peer primary bus 0 frontside bus system memory system memory memory bus pci secondary bus 2 pci/ pci bridge pci/ pci bridge pci/ pci bridge pci/ pci bridge pci secondary bus 3 pci secondary bus 4 video video i/o devices i/o devices disk disk tape tape pci/ scsi bridge pci/ scsi bridge nic adapter nic adapter cpu cpu cpu cpu cpu cpu testcard a b d e host bridge host bridge pci/ pci bridge pci/ pci bridge figure 9. system architecture
11 test method the a gilent system v alidation package allows automatic t ests and stresses data paths from: cpu and exer ciser to system memory exerciser to system memory cpu to exer ciser memory space cpu to exer ciser i/o space peer to peer traffic master to t arget traffic load generation. while testing, the setup emulates typical traffic scenarios in a pci system. for example, data cpu to scsi card, lan to lan card traff ic, concurrent system memory access from lan card and cpu (see f igure 10). so far, these have been typical traffic scenarios and have been generated wit hin the so-called hot mock -up t est. now the agilent verif ication solution signif icantly extends t his validation pr ocess by: increasing t est coverage thr ough increased number of variations, when dealing with system traffic. being prog rammable to force the system?s most critical traffic conditions. being repeat able for failure analysis and failure reg ression tasks. being comparable, to achieve measurable quality improvements. producing log files to catch the problems bef ore the system hangs. creating test reports to document system quality. making an easy link to r&d?s debug envir onment. any access from an a gilent exerciser is per mutated using ppr, varying block sizes, memory commands, alignments, and byte - enables (meaning all variations of dword, word, and byte read/write accesses are used). prot ocol variations on all system actions include waits/lat ency, terminations, 64 bit and 32 bit access, address/data st epping and as well as accept ance/non-accept ance of 64 bit access. automatic test setup when starting the validation software on a system under t est, it automatically scans the system for agilent pci/ pci-x exer ciser and analyzer car ds. based on the available t est cards, the operator can select various tests, def ine the test duration and start the t est. customer configurable tests all tests are conf igurable by the customer. the gui shows all paramet ers, and all setups are simply done with a mouse click. thus, using different exercisers to test between di fferent buses, e.g. 33 mhz pci and mode 2 pci-x, is easy. with each t est, you just select the path to test. the software aut omatically communicates with the t est card plugged into the cor responding bus and t ells you which protocol/traffic paramet ers you may vary. figure 10. test card setup
12 further tests the f ollo wing list describes all tests a vailable for the system validation package. all tests are cust omer configurable (see table 2, page 13), and stress one data path. all t ests can be performed concurrently to i ncrease and maximize stress conditions. the ppr capabilities are customized for the different car ds. for exam ple, different prot ocol variations are available for pci and pci-x. please refer to the cor responding technical data sheet of the exerciser used for a list of available pr otocol variations. cpu and exerciser to system memory (w/r/c data 5 ) access system memory space via virtual memory from cpu and from pci/pci-x bus (exer ciser acting as master). the same address range with int erleaved addresses is used in or der to stress cache contr oller. tested data paths: cpu to host memory; exer ciser to host bridge to system memory. tested devices: host bridge and host bridge conf iguration, host memory contr oller, and arbitration unit. w/r/c to system memory access the system memory from the pci/pci-x bus, and perform data writ e/data read/data com pare. tested data paths: exerciser to host bridge to system memory tested devices: host bridge, host bridge conf iguration, host memory contr oller, and arbitration unit read from memory this t est reads repetitively from a customer -defi ned ph ysical address to check accessibility and to stress the data path: tested data paths: exerciser to host bridge to system memory tested devices: host bridge, host bridge conf iguration, host memory contr oller, and arbitration unit. peer-to-peer traffic (w/r/c data) two pci exer ciser cards access each oth er?s memory or i/o space. master- t arget traffic in both directions is set up. two test cards on different buses are used to test the bridges and bridge configuration. tested data path: exerciser #1 to bridge(s) to ex erciser #2 tested devices: bridges, bridge conf iguration, and arbitration units. master target traffic (w/r/c data) two pci exer ciser cards access each oth er?s memory or i/o space with unidirectional master- target traff ic. two t est cards on diff erent buses are used to test the bridges and bridge conf iguration. tested data path: exerciser #1 to bridge(s) to ex erciser #2 tested devices: bridges, bridge conf iguration, arbitration units cpu to test card (w/r/c data) this t est accesses eit her the test cards memory or i/o space via virtual memory from the cpu. tested data paths: cpu to host bridge to test card tested devices: host bridge, host bridge conf iguration, host memory contr oller, and arbitration unit. bus load generation an exerciser is set up to generate self-traffic and t heref ore saturate a bus with a def ined level of traff ic. this kind of t est stresses other devices on the same bus by limiting the a vailable time a certain device can get access to the bus. also the arbitration unit can be v erif ied under controlled bus load conditions. error analysis the analyzer of an e2920 series test card can be set up to check for: protocol violations data transfer errors parity errors bus hang-ups/bus locks bus load measurements. detected problems are logged in a report f ile. optionally, a trace memory waveform f ile is generated for in-depth r oot cause analysis. all pci/pci-x devices on the bus are passively observed. figure 11. test scenario setup window 5 write/read/compare data
13 in-system programmable the a gilent system validation can be installed and ex ecuted on the syst em-under- t est itself. in this case, the exerciser and anal yzer are programmed through the pci or the pci-x inter face. external control alternatively, the whole t est can also be controlled from an external host pc, which runs the system v alidation package. the exerciser and anal yzer are connected via an appr opriate external interface. to ex ecute a test that r equires the front side interface (fsi, see table 2), the fsi must be installed on the system under t est. working with non-windows os two options are a vailable to v erify a system t hat does not use windows. use an external controlling host pc in this case, any test which does not require the fsi can be ex ecut- ed immediately. to use the other test, the fsi, which is only a small c-program, m ust be com piled for the appr opriate os. the fsi is deliv ered as ex ecut able for windows dos, and in source code. porting the system test library the other altern ative is to import the complete system test library to your preferred os. theref ore, the system t est library comes with source code. table 2. customer configurable test parameter customer configurable test parameters usable mechanisms to detect errors # of fsi 2 band- ppr address address address memory data protocol protocol capture cards width space prefetch size compare check error waveform mask on error 3 cpu and 1 yes 1..100% memory n/a by os 0..512kb/ ??? test card to 0..1mb 1 system memory peer to peer 2 no 1..100% memory true or by bios/ 0..512kb/ ??? test or i/o false os 0..1mb 1 master/target 2 no 1..100% memory true or by bios/ 0..512kb/ ??? traffic or i/o false os 0..1mb 1 cpu to test 1 yes 1..100% memory true or by bios/ 0..512kb/ ??? card or i/o false os 0..1mb 1 write/read/ 1 yes 1..100% memory n/a by os dword ??? compare to value system memory 0..4kbyte read from 1 yes 1..100% memory n/a address dword ??? system memory value value 0..4gbyte bus load 1 no 1..100% memory n/a by bios/ 0..512kb/ ? ?? generation or i/o os 0..1mb 1 (self traffic) 1. the memory can be specified for the selected exerciser. 512kb data memory is available on e2925b, e2928a, and e2940a. 1mb da ta memory is available on e2929b and E2930B 2. the fsi (front side interface) is a small executable table which must run on the system under test cpu(s). 3. requires option 100 for the E2930B.
14 required e2920 series exerciser/analyzer the system validation p ackage requires a full exer ciser/ anal yzer (see table 3). ordering information the system validation package can be ordered as option #310 of the e2925b, e2940a, e2928a, e2929b and E2930B the system t est is also a vailable as a system t est library to be integrated in cust omer pr oprietary test frames. refer to system test library t echnical specif ications (5968-3500e) for m ore information. table 3. minimal exerciser/analyzer configuration needed for option #310/system test library option #310 system test library e2929b/E2930B pci-x protocol checker #300 (exerciser) #320 (c-api) e2925b/e2940a/e2928a pci #300 (exerciser) #320 (c-api) e2922b pci-x master target test cards 1, 2 1. for error detection, the e2922b supports pci-x protocol and data compare only. other analyzing capabilities like waveform capture, trigger i/o, or bus load measures require the e2929b or E2930B. 2. the e2922b does not support external interfaces and must be in-system programmed through pci-x.
15 c-api/ppr (option #320) the optional c-application programming inter face (c-api) provides a prog ramming inter face for setting up and contr olling the exerciser and anal yzer. option #320 comes with a library of c functions to facilitate control of the exerciser and anal yzer. option #320 also comes with a pci protocol permut ation and randomizing library. the test program can run on the syst em-under- t est itself or on an external contr oller. if the program runs on an ext ernal host, the agilent E2930B connects via usb 2.0. if the t est program runs on the syst em-under- t est, the interface itself is used. the library functions are divided into groups, which allow you to set up and control the various capabilities of the agilent E2930B. recommended development environm ent: ms visual c++ v. 6.0 or higher. additional tcl program- ming is possible. agilent patented protocol permutation and randomization (ppr) technology the ppr library extends the c-api by offering dedicated func- tions to setup prot ocol permuta- tion in a pseudo random sequence. it allows easy to set up transf ers of contiguous blocks of data with as many protocol variations as possible. theref ore, the ppr sof tware calculates which variations are cov ered, and after how many data transfers, by permutating the possible prot ocol variations. it determines whether the coverage, within prog rammed constraints, can be achieved under given test cir cumst ances, and calculates the t est time required to perform the data transfers. generating permutations the user -defined protocol constraints can be easily set by specifying lists of prot ocol variations, which must occur. for exam ple, which different burst lengt hs, wait cy cles, memory read/write commands, etc. then, ppr aut omatically moves sequentially through the lists. with each st ep, that is, with each permutation, the next value in this list is combined with the next values in the other lists. the hardware based permut ation proceeds in this way until each value of each list is combined with all values of the other list, and t hus all combinations are covered. in this way, the repetition or omission of combinations is av oided. documented test coverage a print able report t ells you which protocol variation the device has exposed. it explicitly reports which prot ocol attributes are permutated against which other protocol attribut es, and after how many data transfers. optimized test time the values to be varied can be specif ied for each master and target attribute separately. thus, focusing on int eresting cases can optimize t esting time. by carrying out t hese prot ocol permutations in real-time within the exerciser hardware, t hese t ests run much more quickly than any other cpu-based test program.
16 effective test generation the exhaustive c-library makes it simple to focus on t est structuring, par titioning and the specification of prot ocol constraints. this means t hat an appropriate and valuable t est for protocol v erification with meaningful results can quickly be obtained. once start ed, the test can easily be extended to incorporate newly gained experiences or to address t esting needs for newly invented pci-x 2.0 f eatures. deterministic test conditions in contrast to pci-x 2.0 traffic generated by ot her pci-x 2.0 cards, the generated variations are completely deterministic and reproducible. supported protocol variations the exer ciser and anal yzer allow the variation constraints for the transfer, requester and com pleter beha vior to be specif ied. all specif ied constraints can be permutated against each other and up to 100 constraints can be maint ained per list. transfer variations the generator features the follo wing algorit hms: start address alignment; a list of arbitrary address alignments to start transf ers at given offsets (e.g. 1 dword) relative to the qword boundaries byte enables; a list of selected values for the c/be lines during the address phase block size; a block describes a contiguous range in memory available to be transferred. a list of up to 100 diff erent block sizes (from 1 to 4096 byte) can be selected to be transferred bus commands; a list of selected bus commands. all selected commands are permutated with other selected constraints, as appr opriate, for the specif ied transfer direction and specif ications permutation of release or dering bit permutation of no snoop bit. target behavior variations the requester initiator allows for the variation of: byte count (1 to 4096) disconnect/initiator termination delay address st epping req64 release req the com pleter initiator allows for the variation of: error message, yes/no partitioning delay address st epping req64 release req.
17 general specifications specifications: bus: 32/64 bit addressing: 32/64 bit pci clock range: pci: 0-33 mhz pci-x1.0: 0-33 mhz 50-100 mhz 100-133 mhz pci-x 2.0: 50-100 mhz 100-133 mhz timing: the E2930B full y meets electrical and timing specifications for pci- x mode 2. electrical specifications: automatically swit ches between mode 1 for a 3.3v envir onment and mode 2 for a 1.5v accor ding to electrical sprecif ications. power requirements: consumes less t han 25 w from pci-x slot. trace length limits: meets pci-x specifications. signal loading: less t han 10 pf, fully pci-x com pliant. operating tem perature: 0c to +45c. mechanical dimensions: short card, occupying one slot. system requirements: software supports micr osoft windows 2000, 98 and xp. ordering information E2930B base product includes: pci-x state anal yzer 4m samples anal yzer graphical user interface for windows 4m trace memory 4mb/s fast parallel interface 32/64 bit, 133 mhz ddr pci-x mode 2 prot ocol checker usb 2.0 protocol checker graphical user inter face for windows cli inter face tcl interface software media cd option #300, pci-x exerciser includes: customer installable single card license enables on-boar d 32/64 bit, 0..266 mhz exer ciser har dware exerciser graphical user interface for window s software media cd option #310, system validation package (option #300 and option #320 recommended) includes: single card license graphical user inter face for windows . the pci-x exerciser (option #300) must be installed software media cd option #320, c-api / ppr library (option #300 required) cust omer installable single card license enables ppr har dware and c-api interface for one test card the pci-x exer ciser option #300 must be installed driv ers for windows when ordering with out base product, s/n of the existing E2930B must be notif ied on purchase order. accessories external power supply e2991a the exter nal power supply supports applications where the exerciser and analyzer card should be transparent to the syst em, you can connect this external power supply to prevent the card from drawing power from its slot. fast host interface card available as option #400 figure 12. recommended configuration E2930B exerciser & analyzer for pci-x 2.0 mode 1 and mode 2 ddr 266 mt/s gui, protocol checker protocol analyzer option #300 exerciser option #310 svp* option #320 capi
18 overview pci/pci-x e2920 series pci-pci-x bundle with the e2997a agilent also off ers a g reat price on the purchase of the e2928a pci card and the e2929b pci-x card. pci analyzer -protocol checker -64k state pci logic analyzer -4mb fast host interface- timing checker -real-time performance measures- gui - rs 232 interface n/a pci performance optimizer pci exerciser - master and taget- gui - cli -512 kb on-board memory system validation package c-api/ppr e2940a compact pci 32/ 64 bit 66mhz n/a 4m trace memory recommended please order separately 32/64 bit 33 mhz - peer-to-peer -system memory test - systemload test - protocol load test - protocol check - gui - c-programming interface library- protocol permutation and randomization library e2925b pci 32 bit 33 mhz n/a 32 bit 33 mhz e 2928a pci 32/64 bit 66 mhz n/a 32/64 bit 66 mhz 32/64 bit 66 mhz e 2929b pci-x 32/64 bit 133 mhz -protocol checker -rs-232/usb interface - gui pci-x analyzer - 2m state pci logic analyzer - 4mb fast host interface - real-time- performance measures -gui pci-x performance optimizer -post processed and real-time performance analyzer- performance report -gui pci-x exerciser - master - target - gui- 1mb onboard data memory E2930B 32/64 bit 266 mt/s (ddr) -protocol checker -usb 2.0 - gui -state pci logoc analyzer -4mb fast host interface - real time performance measures -gui n/a exerciser for pci-x 2.0 - master- target- gui- 1mb onboard data memory opt100 opt.200 opt.300 opt.320 opt.320 accessories agilent e2940a e2925b e2928a e2929b E2930B products e2991a external - --- power supply e2993a external -- agilent logic analyzer adapter e2994a external -- general purpose logic analyzer adapter e2995a 155 x 4m -- e2996a 155 x 4m -- trace memory
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agilent technologies' test and measurement support, services, and assistance agilent technologies aims to maximize the value you receive, while minimizing your risk and problems. we strive to ensure that you get the test and measurement capabilities you paid for and obtain the support you need. our extensive support resources and services can help you choose the right agilent products for your applications and apply them successfully. every instrument and system we sell has a global warranty. support is available for at least five years beyond the production life of the product. two concepts underlay agilent's overall support policy: "our promise" and "your advantage." our promise our promise means your agilent test and measurement equipment will meet its advertised performance and functionality. when you are choosing new equipment, we will help you with product information, including realistic performance specifications and practical recommendations from experienced test engineers. when you use agilent equipment, we can verify that it works properly, help with product operation, and provide basic measurement assistance for the use of specified capabilities, at no extra cost upon request. many self-help tools are available. your advantage your advantage means that agilent offers a wide range of additional expert test and measurement services, which you can purchase according to your unique technical and business needs. solve problems efficiently and gain a competitive edge by contracting with us for calibration, extra-cost upgrades, out-of- warranty repairs, and on-site education and training, as well as design, system integration, project management, and other professional services. experienced agilent engineers and technicians worldwide can help you maximize your productivity, optimize the return on investment of your agilent instruments and systems, and obtain dependable measurement accuracy for the life of those products. related agilent literature publication number agilent e2925b 32bit, 33 mhz, pci exerciser & analyzer, technical 5968-3501e specifications agilent e2928a 32/64bit, 66 mhz, pci exerciser & analyzer, technical 5968-3506e specifications agilent e2940a compactpci exerciser & analyzer, technical specifications, 5968-1915e agilent e2922b pci-x master target card, technical overview 5968-9577e agilent e2929b pci exerciser & analyzer, technical specifications 5968-8984e agilent system validation pack, agilent system test library, 5968-3500e technical overview agilent technologies e2920, pci series, pci and pci-x design verification, 5968-9694e brochure intel discusses basic concepts of pci performance and efficient use of pci 5988-0448ende with the agilent e2920 series, case study, agilent nsd stabilizes server designs quickly and completely with the agilent 5968-6948e e2920 pci series, case study agilent hstc speeds high-end server testing and reduces engineering costs 5968-6949e with the agilent e2920 pci series, case study, agilent e2920 verification tools, pci series gives altera corporation 5968-4191e competitive advantage, case study, you can find the current literature and software at: www.agilent.com/find/pci_products for more information, please visit us at: www.agilent.com/find/pci_overview by internet, phone, or fax, get assistance with all your test & measurement needs online assistance: www.agilent.com/find/assist phone or fax united states: (tel) 800 452 4844 canada: (tel) 877 894 4414 (fax) (905) 282 6495 china: (tel) 800 810 0189 (fax) 800 820 2816 europe: (tel) (31 20) 547 2323 (fax) (3120) 547 2390 japan: (tel) (81) 426 56 7832 (fax) (81) 426 56 7840 korea: (tel) (88 2) 2004 5004 (fax) (88 2) 2004 5115 latin america: (tel) (305) 269 7500 (fax) (305) 269 7599 taiwan: (tel) 0800 047 866 (fax) 0800 286 331 other asia pacific countries: (tel) (65) 6375 8100 (fax) (65) 6836 0252 email:tm_asia@agilent.com product specifications and descriptions in this document subject to change without notice. copyright ? 2004 agilent technologies printed in germany, april 22nd 2004 5989-0387en www.agilent.com/find/emailupdates get the lat est infor mation on the products and applications you select

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